1. Field of the Invention
The present invention relates to a structure including multiple wire-layers, and particularly to a structure including multiple wire-layers, which is suitable for using in a semiconductor device.
2. Description of the Related Art
FIG. 5 is a schematic cross-sectional view showing a general example of a conventional structure including multiple wire-layers, in which an upper wire-layer and a lower wire-layer are electrically connected to each other via members embedded in via-holes.
As shown in FIG. 5, first wires (in a layer) 112 are provided on an underlying layer 111, and an inter-layer insulating film 120 is provided so as to coat the first wires 112. The inter-layer insulating film 120 comprises a liner insulating film 122 which is provided on the underlying layer 111 and the first wires 112, buried insulating films 124 which are provided on the liner insulating film 122 and respectively between the mutually adjacent first wires 112, and a cap insulating film 126 which is further provided on the buried insulating films 124 and the liner insulating film 122.
Second wires (in a layer) 114 are provided on the inter-layer insulating film 120. Further, via-holes are formed so as to pass through the inter-layer insulating film 120, and the first wires 112 and the second wires 114 are electrically connected to each other via conductive members 117 embedded in the via-holes.
In the above-described conventional structure including multiple wire-layers, because a material having a large dielectric constant within a range from 4.0 to 5.4 is used especially for the buried insulating films, capacitance between the upper wire-layer and the lower wire-layer increases. As a result, operation speed of the semiconductor device using the structure including multiple wire-layers is slowed, and further, electric power consumption and reliability of the semiconductor device are disadvantageously affected.
Further, because of high integration in the semiconductor device based on a refined design rule for an improved fabrication process, capacitance between the mutually adjacent wires in the same layer (fringing capacitance) increases. This also disadvantageously affects the semiconductor device in the above-described manner.
Thus, a structure including multiple wire-layers, in which the capacitance between the wires in different layers and between those in the same layer can be reduced, has been desired.